Algorithms - Zoom-FFT

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The Zoom-FFT is a process where an input signal is mixed down to baseband and then decimated, prior to passing it into a standard FFT. The advantage is for example that if you have a sample rate of 10 MHz and require at least 10Hz resolution over a small frequency band (say 1 KHz) then you do not need a 1 Mega point FFT, just decimate by a factor of 4096 and use a 256 point FFT which is obviously quicker.

Advantages of the Zoom FFT are :

	  Increased frequency domain resolution
	  Reduced hardware cost and complexity
	  Wider spectral range

Applications of the Zoom FFT include :

	  Ultrasonic blood flow analysis
	  R.F. communications
	  Mechanical stress analysis
	  Doppler radar

The following diagram shows the zoom process :

While the following diagram shows the basic architecture of the Zoom-FFT :

One common question is : Is the zoom FFT the same as the chirp z-transform.

The answer is : Absolutely not. The FFT calculates the FFT at N equally spaced points around the unit circle in the z-plane, the chirp z-transform modifies the locations of these points along a contour that can lie anywhere on the z-plane. In contrast, the zoom-FFT uses digital down conversion techniques to localise the standard FFT to a narrow band of frequencies that are centered on a higher frequency. The chirp z-transform is often used to analyze signals such as speech, that have certain frequency domain charactgeristics. The zoom-FFT is used to reduce the sample rate required when analysing narrowband signals - E.G. in HF communications.

Here is a summary of a zoom-fft application that we analyzed.

The application used a 70MHZ CW signal which was sub-sampled at FS=300 MS/s. The frequency range of interest was 69 to 71 MHz with a 500 Hz resolution. This requires a 4096 point FFT over the 2 MHz span, with an equivalent RBW ~36 Hz which required that a Hanning window be applied to the input. The application ran on a PC and was required to interface to several optional post processing graphical environments.

Benchmark Analysis

Required Performace
BW = 2 MHz
Decimation Ratio = 150

The first thing to consider is how much input data is required for the decimation process to take place. In this case the application will require a decimation ration of about 150 or 160 (see later discussion) and with an FFT size of 8192, this means that it will require 160 * 8192 input samples = 1310720.

Using the diagram above for the architecture of the zoom-FFT and the following configuration :
FFT_SIZE   8192L
DECIMATE_RATIO   8L
DECIMATION_FILTER_LENGTH 32L

All of the benchmarks were calculated using data that was captured by the Analog To Digigal Converter (ADC) and processed by the SigLib DLL functions on a P4M laptop running Windows XP. The benchmark figures were calculated using the Pentium Time Slot Counter which gives an accurate count of the number of cycles that a piece of code takes to execute. The Time Slot Counter is a very high performance benchmarking facility in Pentium class processors and is CPU clock speed independent. Obviously a 1 GHz processor will be execute 1x10^9 instructions in 1 second so using this and the sum of all the cycles means that you should be able to get a pretty accurate idea of how quickly the code will execute.

For this application, the function required 6799608 clock cycles to run.

The 8192 point FFT required 4212956 cycles, which meant that the decimation stage required 6799608 - 4212956 = 2586652 cycles. The input stream was 8192 * 8 samples = 65536. I.e. 39.4 cycles per input point. For this application it will require 8192 * 160 = 1310720 samples so this will take 51733040 cycles.

For this application a first stage decimation of a factor of 8 is a good choice but it will then need to place some FIR decimating filters between the comb decimating filters and the FFT. The ideal decimation ratio is 150 however using a factor of 8 at the front end requires a final decimation ratio of 18.75, which is not very practical so a better solution for the FIR decimation stage would be 20, giving an overall ratio of 160. Another option would be to use a ratio of 18, giving an overall ratio of 144. To implement an FIR filter with a decimation ratio of 18 or 20 will require approximately 150 coefficients and the zoom-FFT will require two of these - one for the I channel and one for the Q.

To benchmark the FIR decimation stage a 150 coefficient FIR filter was analyzed while processing 512 samples and this took 262300 cycles. I.e. 512 cycles per input point or 3.4 cycles per coefficient. For this application, if we assume the worst case (decimation ratio 20) then the required number of input samples will be 8192 * 20, which equals 163840 and this will require 163840 * 512 cycles = 83936000 cycles per path. For the two paths this means that the FIR filtering will require 167872000 cycles.

The final result therefore is :
First Decimation stage      51733040
FIR decimation stage      167872000
FFT                                        4212956
                                           =========
Total benchmark               223817996 cycles or 0.22 seconds on a 1 GHz machine

SUMMARY
While it would be entirely possible to optimize this code using assembly to get higher performance, the ANSI C coded SigLib DSP library is often quite capable of implementing high performance real-time systems.

These algorithms are included for information and are by no means definitive descriptions. If you would like to add anything to these pages then please feel free to email me and I will add your information, with my thanks.

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